The present invention relates to a semiconductor circuit device of which transistor ability is enhanced by optimization of design layout and a simulation method thereof.
Recently, LSI (Large Scale Integrated) circuits typified by microprocessors are configured by combination of multiple unit circuits generally called cells and having a fundamental function. Meanwhile, in association with increases in performance and in integration of the LSI circuits, the importance of a role is increasing which CAD (Computer Aided Design) tools play in highly accurate circuit design of cells that form the basis of the LSI circuits.
As one of CAD tools on which layout accuracy largely depends, a circuit simulator is listed. The circuit simulator performs simulation on a designed cell or LSI circuit on the assumption of operation of an actually manufactured cell or LSI circuit on the basis of a netlist containing connection information on respective elements such as a MIS (metal insulator semiconductor) transistor, a capacitor, a resistor, and the like and characteristic information on each element, such as transistor size (transistor width and transistor length), capacitance, resistance, and the like.
The netlist is generated by extracting the characteristic information and the connection information of each arranged element, for example, from mask layout data of the designed cell by a layout parameter extractor (LPE).
For reproducing a complicated electric characteristic of a MIS transistor on such a circuit simulator at high accuracy, various kinds of electric characteristic formulae (hereinafter referred to as transistor models) are developed as characteristic information of the MIS transistor. In order to reproduce a desired transistor characteristic from a transistor model, it is necessary to optimize a model parameter included in the transistor model (hereinafter referred to as extraction of a model parameter) so as to match a desired transistor characteristic.
A layout of a conventional semiconductor circuit device and a transistor model used in a conventional design process of a semiconductor circuit device will be described below.
First, the layout of the semiconductor circuit device will be described by referring to an example of a cell layout shown in FIG. 7.
As shown in FIG. 7, a first PMIS transistor 120 formed on a semiconductor substrate (not shown) includes a first active region 101 and a first gate electrode 104 having a protruding portion 103 while a first NMIS transistor 121 includes a second active region 102 and a second gage electrode 105 having a protruding portion 103. The first gate electrode 104 and the second gate electrode 105 are connected to each other by means of a first gate wiring 106.
Similarly, a second PMIS transistor 130 includes a third active region 107 and a third gate electrode 109 having a protruding portion 103 while a second NMIS transistor 131 includes a fourth active region 108 and a fourth gage electrode 110 having a protruding portion 103. The third gate electrode 109 and the fourth gate electrode 110 are connected to each other by means of a second gate wiring 111.
Herein, the gate width Wp2 of the second PMIS transistor 130 is smaller than the gate width Wp1 of the first PMIS transistor 120. Similarly, the gate width Wn2 of the second NMIS transistor 131 is smaller than the gate width Wn1 of the first NMIS transistor 121. Also, the lengths E the protruding portions 103 of the gate electrodes of the respective transistors 120, 121, 130, 131 have the same length E. This is because: when the length E of each protruding portion 103 is set the shortest, capacitance caused between each gate electrode and the semiconductor substrate can be reduced with a result that propagation delay time of the cell can be shortened to the most unless the gate electrodes themselves are used as wirings for connection to another device.
Referring to a pair of the first PMIS transistor 120 and the first NMIS transistor 121 and a pair of the second PMIS transistor 130 and the second NMIS transistor 131, the gate widths Wp1, Wpp2 of the PMIS transistors 120, 130 are greater than the gate widths Wn1, Wn2 of the NMIS transistors 121, 131, respectively. This arrangement is set on the basis that current drivability per unit gate width is lower in the PMIS transistor than in the NMIS transistor. With the gate width of the PMIS transistor greater than the gate width of the NMIS transistor, in a generally-called CMIS (complementary MIS) transistor composed of such a pair of the PMIS transistor and the NMIS transistor, when the potential level of an input signal is changed from HIGH to LOW, signal propagation time required for changing the level of an output signal from LOW to HIGH can be shortened more as the PMIS transistor has higher current drivability, resulting in realization of a higher performance semiconductor circuit device.
A transistor model used in the conventional semiconductor circuit design will be described next by referring to an example of a schematic view of FIG. 8.
FIG. 8 is a schematic view showing one example of a layout of a MIS transistor. As shown in FIG. 8, the MIS transistor is formed of an active region 112 and a gate electrode 113 arranged thereon. In a transistor model, a channel 114 of the MIS transistor is defined as an overlap region (a hatched part) of the active region 112 and the gate electrode 113.
In general, in the transistor model, the current drivability of the transistor is determined according to the width W and the length L of the channel 114, the resistance of the active region 112, and the resistance to be added to the active region 112 (not shown). Wherein, though information relating to a layout in the peripheral region of the transistor has not been taken into consideration conventionally, a transistor model using the lengths SA, SB of the active region as parameters has been developed for additionally reflecting characteristic variation caused due to STI (shallow trench isolation) stress (see Japanese Patent Application Laid Open Publication No. 2003-264242A, for example).
A netlist and a layout parameter extractor used in the conventional semiconductor circuit design will be described below with reference to FIG. 9 and FIG. 10.
FIG. 9 shows one example of a netlist for circuit simulation which indicates characteristic information and connection information of elements composing a semiconductor circuit device. In the netlist 140 shown in FIG. 9, each row beginning with “M” is description of a MIS transistor and indicates MIS transistor recognition information, terminal connection information of a drain, a gate, a source, and a substrate, a name of a MIS transistor model, a gate width, and a gate length in this order from the left. Wherein, each unit “u” at the gate width and the gate length is “μm.”
FIG. 10 is a block diagram showing the conventional layout parameter extractor. As shown in FIG. 10, the layout parameter extractor 141 receives, as an input, mask layout data 143 of a semiconductor circuit device to be designed and extracts circuit connection information at a circuit element recognition section 142. Specifically, it recognizes a MIS transistor and outputs the terminal connection information and the transistor size of the thus recognized MIS transistor to the netlist 140.
However, in the conventional layout method as shown in FIG. 7 in which the gate widths of the PMIS transistors are set wider than those of the NMIS transistors for supplementing the current drivability of the PMIS transistors, the gate capacity increases as the current drivability of the PMIS transistor increases. This means that an effect of shortening the signal propagation time by the increase in current drivability cannot be expected necessarily.